This application is based on and incorporates herein by reference Japanese Patent Application No. 2001-144884 filed on May 15.
1. Field of the Invention
The present invention relates to a semiconductor device, which includes a diaphragm having a desired flatness, and to a method for manufacturing the device. The diaphragm is formed on a semiconductor substrate using semiconductor fabrication technology.
2. Related Art
A diaphragm-type semiconductor device, a cross-sectional view of which is shown in FIG. 1, is proposed in JP-A-2000-214035. In the proposed device, a circular bottom electrode layer 4 is located in a silicon substrate 2. A bottom etch-proof layer 8 is located on the substrate 2. A middle etch-proof layer 12 is located on the bottom etch-proof layer 8. A circular pressure reference space 28, which is coaxial with the bottom electrode layer 4, is defined by the etch-proof layers 12, 8. A circular top electrode layer 14, which is smaller than the pressure reference space 28 and has a hole 14b, is located on the middle etch-proof layer 12. As shown in FIG. 2, the top electrode layer 14 is coaxial with the pressure reference space 28. A terminal 14a for electrical connection is integrated with the top electrode layer 14. A top etch-proof layer 16 is located on the top electrode layer 14 and the middle etch-proof layer 12. A diaphragm 27 includes the middle etch-proof layer 12, the top electrode layer 14, and the top etch-proof layer 16. The diaphragm 27 has a hole 17, which is formed in the middle and top etch-proof layers 12 and 16. The hole 17 of the diaphragm 27 is sealed with a shield film 24.
The diaphragm 27 is deformed in response to external pressure applied to the diaphragm 27. When the diaphragm 27 is deformed, the distance between the top and bottom electrode layers 14, 4, is varied, and so is the static capacitance between the top and bottom electrode layers 14, 4. Therefore, the external pressure is sensed by measuring the capacitance between the top and bottom electrode layers 14 and 4.
The proposed device is manufactured by processing the silicon substrate 2 using a microchip manufacturing process, as shown FIGS. 3 to 6. First, the bottom electrode layer 4 is formed in a surface of the substrate 2 by doping a predetermined region in the surface with impurity ions. After depositing the bottom etch-proof layer 8 on the surface of the substrate 2, a circular etchable layer 10 (see FIG. 3), which is coaxial with the bottom electrode layer 4, is formed on the bottom etch-proof layer 8. After depositing the middle etch-proof layer 12 on the etchable layer 10 and the surface, a polycrystalline silicon layer is deposited on the middle etch-proof layer 12 and doped with impurity ions. Then, the top electrode layer 14, which is coaxial with the bottom electrode layer 4 and has the hole 14b, is defined by photolithography. Then, the top etch-proof layer 16 is deposited on the top electrode layer 14 and the middle etch-proof layer 12. At this stage, the device has the cross-sectional structure shown in FIG. 3
The hole 17 of the diaphragm 27 is formed in the middle and top etch-proof layers 12, 16 to permit the etchable layer 10 to communicate with the space outside of the device, as shown in FIG. 4. Subsequently, the etchable layer 10 is removed by etching the layer 10 through the hole 17 of the diaphragm 27 to form the diaphragm 27 and the pressure reference space 28, as shown in FIG. 5. Finally, the shield film 24 is deposited on the top etch-proof layer 16 to seal the hole 17 of the diaphragm 27, as shown FIG. 6.
It is preferred that the diaphragm 27 be flat and parallel to the surface of the silicon substrate 2, as shown in FIG. 1. However, as shown in FIG. 5, the diaphragm 27 is warped toward the surface. The measured flatness of the diaphragm 27 is shown in FIG. 15. In FIG. 15, a line AA shows the flatness after the etchable layer 10 is removed as shown in FIG. 5, and a line BB shows the flatness after the shield film 24 is deposited by plasma CVD as shown in FIG. 6, and a line CC shows the flatness when a pressure of 100 KPa is applied to the proposed device. Due to the warping of the diaphragm 27, the static capacitance between the top electrode layer 14 and the bottom electrode layer 4 is not proportional to the external pressure applied to the diaphragm 27. In the worst case, the diaphragm 27 contacts the surface, and the device is useless for sensing pressure.
In addition, the capacitance between the top and bottom electrode layers 14, 4 is affected by temperature in the proposed device. Therefore, the external pressure is not accurately measured unless the temperature is constant.
The present invention has been made in view of the above aspect with an object to provide a diaphragm-type semiconductor device, which has a desired linearity between static capacitance and external pressure and detects accurately the external pressure irrespective of temperature, and to provide a method for manufacturing the device. The desired linearity between static capacitance and external pressure is provided by forming a diaphragm with a desired flatness. The external pressure is detected accurately irrespective of temperature by building a reference capacitor in the device.
In the present invention, a circular top electrode layer is larger than a circular pressure reference space and is coaxial with the space. Therefore, internal stress is balanced between inner and outer sides of a diaphragm, and a step, which is formed at the outer edge of the top electrode layer and where the internal stress is concentrated, is separated from the diaphragm. Thus, the diaphragm is substantially flat.
In addition, a step adjuster is formed around the pressure reference space. Therefore, another step, which is formed at the outer edge of the pressure reference space and where the internal stress is concentrated, disappears, and a new step, which is separated from the diaphragm, is formed at the outer edge of the step adjuster. Thus, the diaphragm has a further desired flatness.
A reference capacitor, which has no pressure reference space, is built in the device. The capacitance of the capacitor depends only on temperature, not on pressure. A capacitance shift between the top electrode layer and a corresponding bottom electrode layer due to temperature variation is compensated for with the reference capacitor.